1. Field of the Invention
The present invention relates, in general, to a data output circuit of a synchronous memory device, and more particularly, to a data output circuit which determines an output sequence of data outputted to the outside of a memory device, depending upon a column address applied by a read command and a burst type.
2. Description of the Related Art
As is generally known in the art, in a synchronous memory device (hereinafter, referred to as a “memory device”), the data read out from a memory cell in response to a read command is amplified by a sense amplifier, is transmitted to a global bus line, and then is outputted to the outside through a pipelatch and an output driver. In this regard, the present invention lays emphasis on a method for processing data applied to the pipelatch. This method will be explained in detail below with reference to FIGS. 1 and 2.
FIG. 1 illustrates an example of a data output circuit of a conventional memory device, in particular, an example of a data output circuit having a 4 bits prefetch function. FIG. 2 is a table explaining a data output sequence determined depending upon the lower 2 bits of a column address (a starting column address) applied by a read command and a data output mode (an interleave mode or a sequential mode).
In FIG. 1, gio1<0:3>, gio2<0:3>, gio3<0:3> and gio4<0:3> represent different global bus lines. The respective global bus lines transmit 4 bits data q<0:3> to respective corresponding pipelatches 101, 102, 103 and 104.
The respective pipelatches 101, 102, 103 and 104 receive their corresponding enable signals PIN1, PIN2, PIN3 and PIN4 and a plurality of control signals ctr1, ctr2, ctr3 and ctr4.
The output signals of the respective pipelatches are inputted to a pre-driver 105. The data inputted to the pre-driver 105 are synchronized with synchronization signals rclk_do and fclk_do and then transmitted to an output driver (not shown). Here, the synchronization signals rclk_do and fclk_do are internal clock signals which are outputted from a DLL circuit in a synchronous memory device.
FIG. 3 is a concrete example of the pipelatch 101 shown in FIG. 1. For reference, the pipelatches 102, 103 and 104 are configured in the same manner as the pipelatch 101.
Referring to FIG. 3, an input terminal in1 receives data q0, an input terminal in2 receives data q1, an input terminal in3 receives data q2, and an input terminal in4 receives data q3. The data q0 through q3 represent the data applied to the pipelatch through the global bus line.
A signal soseb0 is an abbreviation of a “start odd start even bar,” and the logical value of the signal soseb0 is determined by the value of the lowermost 2 bits of a column address (hereinafter, referred to as a “starting column address”) applied by a read command and a data output sequence mode (see FIG. 2). For reference, the data output sequence mode is a mode for determining a data output sequence and includes a sequential mode and an interleave mode.
The enable signal PIN1 is a signal which determines whether a buffer for receiving the data q0 through q3 is to be enabled or not.
A signal soseb1_r and a signal soseb1_f are switching signals. The signal soseb1_r determines an output sequence of the data having passed through a node pre_rdo<0> and the data having passed through a node pre_rdo<1>. The signal soseb1_f determines an output sequence of the data having passed through a node pre_fdo<0> and the data having passed through a node pre_fdo<1>.
A signal rpout and a signal fpout are signals for enabling the output buffers of the pipelatch. The data on the nodes pre_rdo<0>, pre_rdo<1>, pre_fdo<0> and pre_fdo<1> are outputted through the output nodes rdo and fdo of the output buffers of the pipelatch.
In operation, for example, as shown in FIG. 2, when a starting address is “00” under the sequential mode, the signal soseb0 has a low level. In this case, as can be readily seen from FIGS. 2 and 3, the data q0 is outputted through the node pre_rdo<0>, the data q2 is outputted through the node pre_rdo<1>, the data q1 is outputted through the node pre_fdo<0>, and the data q3 is outputted through the node pre_fdo<1>.
Next, when the signal soseb1_r has a low level, the data q0 on the node pre_rdo<0> is transmitted to the node rdo through the output buffer, and when the signal soseb1_r has a high level after 1tCK, the data q2 on the node pre_rdo<1> is transmitted to the node rdo through the output buffer. Here, 1tCK means a cycle of a clock signal used in the synchronous memory device.
Similarly, when the signal soseb1_f is a low level, the data q1 on the node pre_fdo<0> is transmitted to the node fdo through the output buffer, and when the signal soseb1_f is a high level after 1tCK, the data q3 on the node pre_fdo<1> is transmitted to the node fdo through the output buffer. At this time, since the signal soseb1_f operates later than the signal soseb1_r with a delay of ½tCK, the data applied to the pre-driver 105 of FIG. 1 are applied in the sequence of q0, q1, q2 and q3. That is to say, when the starting column address is 0 and the sequential mode is used, the data applied to the pre-driver are applied in the sequence of q0, q1, q2 and q3.
In another example, when the starting column address is 3 under the interleave mode, the data q1 is transmitted to the node pre_rdo<0>, the data q3 is transmitted to the node pre_rdo<1>, the data q0 is transmitted to the node pre_fdo<0>, and the data q2 is transmitted to the node pre_fdo<1>. In this case, the signal soseb1_r maintains a high level at the start and maintains a low level after 1tCK. Also, the signal soseb1_f which is outputted later than the signal soseb1_r with a delay of ½tCK maintains a high level at the start and maintains a low level after 1tCK. Accordingly, the data q3 and q1 are sequentially outputted through the node rdo, and the data q2 and q0 are sequentially outputted through the node fdo. As a result, the data are applied to the pre-driver in the sequence of q3, q2, q1 and q0.
The operation of each of the remaining pipelatches 102 through 104 shown in FIG. 1 is the same as that explained with respect to FIG. 3. However, depending upon the enable timings of the enable signals PIN2, PIN3 and PIN4 applied to the respective pipelatches 102 through 104, the operation times of the pipelatches are differentiated. Generally, since the output nodes rdo and fdo of the pipelatches shown in FIG. 1 are commonly used, the enable signals PIN1 through PIN4 are sequentially enabled without being overlapped with one another and operate the respective pipelatches. For reference, the data outputted from the circuit of FIG. 1 and applied to the data output buffer (not shown) is outputted to the outside through one data pin. Therefore, when the number of the data pins is N, it means that the circuit of FIG. 1 exists in the number of N.
The signals soseb1_r, soseb1_f, rpout and fpout described with respect to FIG. 3 are independent signals individually applied to the respective pipelatches. Hence, while not shown in the drawings, the circuits for generating the signals soseb1_r, soseb1_f, rpout and fpout transmit the signals to the pipelatches using 16 signal lines.
However, as described above, since the respective pipelatches which constitute the conventional data output circuit explained with respect to FIGS. 1 and 3 use the independent signals soseb1_r, soseb1_f, rpout and fpout corresponding to them, it is essential to locate the signal lines for transmitting these signals. For example, when the number of data pins is N, 16×N signal lines are located. As a consequence, a problem is caused in that the layout efficiency of a highly integrated memory device is deteriorated.